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| Features * High Performance, Low Power AVR (R) 8-bit Microcontroller * Advanced RISC Architecture - 131 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 1 MIPS throughput per MHz - On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory - 8K Bytes Flash of In-System Programmable Program Memory * Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 512 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 512 Bytes Internal SRAM - Programming Lock for Flash Program and EEPROM Data Security On Chip Debug Interface (debugWIRE) Peripheral Features - Two 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement * Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time * Variable PWM duty Cycle and Frequency * Synchronous Update of all PWM Registers * Auto Stop Function for Event Driven PFC Implementation * Less than 25 Hz Step Width at 150 kHz Output Frequency * PSC2 with four Output Pins and Output Matrix - One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode - One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode - Master/Slave SPI Serial Interface - 10-bit ADC * 8 Single Ended Channels and 1 Fully Differential ADC Channel Pair * Programmable Gain (5x, 10x, 20x, 40x on Differential Channel) * Internal Reference Voltage - Two Analog Comparator with Resistor-Array to Adjust Comparison Voltage - 4 External Interrupts - Programmable Watchdog Timer with Separate On-Chip Oscillator Special Microcontroller Features - Low Power Idle, Noise Reduction, and Power Down Modes - Power On Reset and Programmable Brown Out Detection - Flag Array in Bit-programmable I/O Space (4 bytes) - In-System Programmable via SPI Port - Internal Calibrated RC Oscillator ( 8 MHz) - On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) * * * * * * 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM1 Summary * 4378CS-AVR-09/08 * Operating Voltage: 2.7V - 5.5V * Extended Operating Temperature: - -40C to +105 1. History Product AT90PWM1 Revision First revision of parts 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3. Pin Configurations Figure 3-1. SOIC 24-pin Package 2 AT90PWM1 4378CS-AVR-09/08 4378CS-AVR-09/08 Figure 3-2. (PSCIN2/OC1A/MISO_A) PD2 (OC0A/SS/MOSI_A) PD3 NC VCC GND NC NC (MISO/PSCOUT20) PB0 QFN 32 -pin Package 1 2 3 4 5 6 7 8 PD1(PSCIN0/CLKO) PE0 (RESET/OCD) NC PD0 (PSCOUT00/SS_A) AT90PWM1 QFN 32 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/ICP1_A/SCK_A) PD4 (ADC2/ACMP2 ) PD5 (ADC3/ACMPM/INT0) PD6 (ACMP0) PD7 (ADC5/INT1) PB2 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 PB7 (ADC4/PSCOUT01/SCK) PB6 (ADC7/ICP1B) PB5 (ADC6/INT2) NC 24 23 22 21 20 19 18 17 PB4 (AMP0+) PB3 (AMP0-) NC AREF AGND AVCC NC NC AT90PWM1 3 3.1 Pin Descriptions : Table 3-1. QFN32 5 20 4 Pin out description S024 Pin Number 7 18 6 Mnemonic GND AGND VCC Type Power Power power Name, Function & Alternate Function Ground: 0V reference Analog Ground: 0V reference for analog part Power Supply: Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog MISO (SPI Master In Slave Out) PSCOUT20 output MOSI (SPI Master Out Slave In) PSCOUT21 output ADC5 (Analog Input Channel5 ) INT1 AMP0- (Analog Differential Amplifier 0 Input Channel ) AMP0+ (Analog Differential Amplifier 0 Input Channel ) ADC6 (Analog Input Channel 6) INT 2 ADC7 (Analog Input Channel 7) 19 17 AVCC Power 21 19 AREF Power 8 8 PBO I/O 9 9 PB1 I/O 16 23 24 26 16 20 21 22 PB2 PB3 PB4 PB5 I/O I/O I/O I/O 27 23 PB6 I/O ICP1B (Timer 1 input capture alternate input) PSCOUT11 output PSCOUT01 output 28 24 PB7 I/O ADC4 (Analog Input Channel 4) SCK (SPI Clock) PSCOUT00 output 29 1 PD0 I/O XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) 32 3 PD1 I/O PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) PSCIN2 (PSC 2 Digital Input) 1 4 PD2 I/O OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate SPI Master In Slave Out) TXD (Dali/UART Tx data) 2 5 PD3 I/O OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) 4 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 Table 3-1. QFN32 Pin out description (Continued) S024 Pin Number Mnemonic Type Name, Function & Alternate Function ADC1 (Analog Input Channel 1) 12 12 PD4 I/O RXD (Dali/UART Rx data) ICP1A (Timer 1 input capture) SCK_A (Programming & alternate SPI Clock) 13 13 PD5 I/O ADC2 (Analog Input Channel 2) ACMP2 (Analog Comparator 2 Positive Input ) ADC3 (Analog Input Channel 3 ) 14 14 PD6 I/O ACMPM reference for analog comparators INT0 15 31 15 2 PD7 PE0 I/O I/O or I ACMP0 (Analog Comparator 0 Positive Input ) RESET (Reset Input) OCD (On Chip Debug I/O) XTAL1: XTAL Input OC0B (Timer 0 Output Compare B) XTAL2: XTAL OuTput ADC0 (Analog Input Channel 0) 10 10 PE1 I/O 11 11 PE2 I/O 4. Overview The AT90PWM1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 5 4378CS-AVR-09/08 4.1 Block Diagram Figure 4-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90PWM1 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, 2 Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, an 8-channel 10-bit ADC with two differential 6 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90PWM1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM1 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4.2 4.2.1 Pin Descriptions VCC Digital supply voltage. 4.2.2 GND Ground. 4.2.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90PWM1 as listed on page 65. 4.2.4 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM1 as listed on page 68. 7 4378CS-AVR-09/08 4.2.5 Port E (PE2..0) RESET/ XTAL1/ XTAL2 Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page 43. Shorter pulses are not guaranteed to generate a Reset. Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier. The various special features of Port E are elaborated in "Alternate Functions of Port E" on page 71 and "Clock Systems and their Distribution" on page 27. 4.2.6 AVCC AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 4.2.7 AREF This is the analog reference pin for the A/D Converter. 4.3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 8 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 5. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name PICR2H PICR2L PFRC2B PFRC2A PCTL2 PCNF2 OCR2RBH OCR2RBL OCR2SBH OCR2SBL OCR2RAH OCR2RAL OCR2SAH OCR2SAL POM2 PSOC2 PICR1H PICR1L PFRC1B PFRC1A PCTL1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PSOC1 PICR0H PICR0L PFRC0B PFRC0A PCTL0 PCNF0 OCR0RBH OCR0RBL OCR0SBH OCR0SBL OCR0RAH OCR0RAL OCR0SAH OCR0SAL Reserved PSOC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page page 162 page 162 PCAE2B PCAE2A PPRE21 PFIFTY2 PISEL2B PISEL2A PPRE20 PALOCK2 PELEV2B PELEV2A PBFM2 PLOCK2 PFLTE2B PFLTE2A PAOC2B PMODE21 PRFM2B3 PRFM2A3 PAOC2A PMODE20 PRFM2B2 PRFM2A2 PARUN2 POP2 PRFM2B1 PRFM2A1 PCCYC2 PCLKSEL2 PRFM2B0 PRFM2A0 PRUN2 POME2 page 161 page 161 page 160 page 157 page 157 page 157 page 157 page 157 page 156 page 156 page 156 page 156 POMV2B3 POS23 POMV2B2 POS22 POMV2B1 PSYNC21 POMV2B0 PSYNC20 POMV2A3 POEN2D POMV2A2 POEN2B POMV2A1 POEN2C POMV2A0 POEN2A page 163 page 155 PCAE1B PCAE1A - - - - - - - - - - - PISEL1B PISEL1A - - - - - - - - - - - PELEV1B PELEV1A - - - - - - - - - - PSYNC11 PFLTE1B PFLTE1A - - - - - - - - - - PSYNC10 PRFM1B3 PRFM1A3 - - - - - - - - - - - PRFM1B2 PRFM1A2 - - - - - - - - - - POEN1B PRFM1B1 PRFM1A1 - - - - - - - - - - - PRFM1B0 PRFM1A0 PRUN1 - - - - - - - - - - POEN1A page 161 page 161 page 160 page 162 page 162 PCAE0B PCAE0A PPRE01 PFIFTY0 PISEL0B PISEL0A PPRE00 PALOCK0 PELEV0B PELEV0A PBFM0 PLOCK0 PFLTE0B PFLTE0A PAOC0B PMODE01 PRFM0B3 PRFM0A3 PAOC0A PMODE00 PRFM0B2 PRFM0A2 PARUN0 POP0 PRFM0B1 PRFM0A1 PCCYC0 PCLKSEL0 PRFM0B0 PRFM0A0 PRUN0 page 161 page 161 page 158 page 157 page 157 page 157 page 157 page 157 page 156 page 156 page 156 page 156 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PSYNC01 - - - - - - - - - - - - - - - - - - PSYNC00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - POEN0B - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - POEN0A - - - - - - - - - - - - - - - - - page 155 9 4378CS-AVR-09/08 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC2CON AC0CON Reserved Reserved Reserved Reserved Reserved Reserved Reserved PIM2 PIFR2 Reserved Reserved PIM0 PIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved Bit 7 - - - - - - - - - - - - - - - AC2EN AC0EN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OCR1B15 OCR1B7 OCR1A15 OCR1A7 ICR115 ICR17 TCNT115 TCNT17 - FOC1A ICNC1 COM1A1 - ADC7D - Bit 6 - - - - - - - - - - - - - - - AC2IE AC0IE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OCR1B14 OCR1B6 OCR1A14 OCR1A6 ICR114 ICR16 TCNT114 TCNT16 - FOC1B ICES1 COM1A0 - ADC6D - Bit 5 - - - - - - - - - - - - - - - AC2IS1 AC0IS1 - - - - - - - PSEIE2 PSEI2 - - PSEIE0 PSEI0 - - - - - - - - - - - - - - - - - - - - OCR1B13 OCR1B5 OCR1A13 OCR1A5 ICR113 ICR15 TCNT113 TCNT15 - - - COM1B1 ACMP0D ADC5D - Bit 4 - - - - - - - - - - - - - - - AC2IS0 AC0IS0 - - - - - - - PEVE2B PEV2B - - PEVE0B PEV0B - - - - - - - - - - - - - - - - - - - - OCR1B12 OCR1B4 OCR1A12 OCR1A4 ICR112 ICR14 TCNT112 TCNT14 - - WGM13 COM1B0 AMP0PD ADC4D - Bit 3 - - - - - - - - - - - - - - - AC2SADE- - - - - - - PEVE2A PEV2A - - PEVE0A PEV0A - - - - - - - - - - - - - - - - - - - - OCR1B11 OCR1B3 OCR1A11 OCR1A3 ICR111 ICR13 TCNT111 TCNT13 - - WGM12 - AMP0ND ADC3D/ACMPMD - Bit 2 - - - - - - - - - - - - - - - AC2M2 AC0M2 - - - - - - - PRN21 - - PRN01 - - - - - - - - - - - - - - - - - - - - OCR1B10 OCR1B2 OCR1A10 OCR1A2 ICR110 ICR12 TCNT110 TCNT12 - - CS12 - ADC10D/ACMP1D ADC2D/ACMP2D - Bit 1 - - - - - - - - - - - - - - - AC2M1 AC0M1 - - - - - - - PRN20 - - PRN00 - - - - - - - - - - - - - - - - - - - - OCR1B9 OCR1B1 OCR1A9 OCR1A1 ICR19 ICR11 TCNT19 TCNT11 - - CS11 WGM11 ADC9D/AMP1PD ADC1D - Bit 0 - - - - - - - - - - - - - - - AC2M0 AC0M0 - - - - - - - PEOPE2 PEOP2 - - PEOPE0 PEOP0 - - - - - - - - - - - - - - - - - - - - OCR1B8 OCR1B0 OCR1A8 OCR1A0 ICR18 ICR10 TCNT18 TCNT10 - - CS10 WGM10 ADC8D/AMP1ND ADC0D - Page page 178 page 177 page 258 page 258 page 257 page 164 page 164 page 164 page 164 page 120 page 120 page 120 page 120 page 121 page 121 page 120 page 120 page 119 page 118 page 116 page 199 page 199 10 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) AMP0CSR Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved Reserved Reserved Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR MSMCR MONDR ACSR Reserved SPDR SPSR SPCR Reserved Reserved PLLCSR OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR GPIOR3 ACCKDIV - SPD7 SPIF SPIE - - OCR0B7 OCR0A7 TCNT07 FOC0A COM0A1 TSM - EEAR7 EEDR7 - GPIOR07 - - GPIOR37 AC2IF - SPD6 WCOL SPE - - OCR0B6 OCR0A6 TCNT06 FOC0B COM0A0 ICPSEL1 - EEAR6 EEDR6 - GPIOR06 - - GPIOR36 - - SPD5 - DORD - - OCR0B5 OCR0A5 TCNT05 - COM0B1 - - EEAR5 EEDR5 - GPIOR05 - - GPIOR35 AMP0EN - - - - - - - - - - - - ISC31 - - - - PRPSC2 - - CLKPCE WDIF I SP15 SP7 - - - - - SPMIE - SPIPS - - - - - - - - - - - - - - ISC30 - - CAL6 - PRPSC1 - - - WDIE T SP14 SP6 - - - - - RWWSB - - - - AMP0G1 - - - - - - ICIE1 - - - - - ISC21 - - CAL5 - PRPSC0 - - - WDP3 H SP13 SP5 - - - - - - - - - - AMP0G0 - - - - - - - - - - - - ISC20 - - CAL4 - PRTIM1 - - - WDCE S SP12 SP4 - - - - - RWWSRE - PUD - - - - - - - - - - - - - - ISC11 - - CAL3 - PRTIM0 - - CLKPS3 WDE V SP11 SP3 - - - - - BLBSET - - WDRF SM2 AMP0TS2 - - - - - - OCIE1B OCIE0B - - - - ISC10 - - CAL2 - PRSPI - - CLKPS2 WDP2 N SP10 SP2 - - - - - PGWRT - - BORF SM1 AMP0TS1 - - - - - - OCIE1A OCIE0A - - - - ISC01 - - CAL1 - - - - CLKPS1 WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF SM0 AMP0TS0 - - - - - - TOIE1 TOIE0 - - - - ISC00 - - CAL0 - PRADC - - CLKPS0 WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE page 56 & page 65 page 46 page 37 reserved reserved AC2O - SPD2 - CPHA - - PLLF OCR0B2 OCR0A2 TCNT02 CS02 - - EEAR10 EEAR2 EEDR2 EEMWE GPIOR02 INT2 INTF2 GPIOR32 - - SPD1 - SPR1 - - PLLE OCR0B1 OCR0A1 TCNT01 CS01 WGM01 - EEAR9 EEAR1 EEDR1 EEWE GPIOR01 INT1 INTF1 GPIOR31 AC0O - SPD0 SPI2X SPR0 - - PLOCK OCR0B0 OCR0A0 TCNT00 CS00 WGM00 PSRSYNC EEAR8 EEAR0 EEDR0 EERE GPIOR00 INT0 INTF0 GPIOR30 page 33 page 94 page 93 page 93 page 92 page 89 page 77 page 19 page 19 page 20 page 20 page 25 page 75 page 75 page 25 page 174 page 173 page 172 page 179 page 211 page 35 page 50 page 11 page 13 page 13 page 39 page 31 page 74 page 121 page 94 page 202 Name ADMUX ADCSRB ADCSRA ADCH ADCL Bit 7 REFS1 ADHSM ADEN - / ADC9 ADC7 / ADC1 Bit 6 REFS0 - ADSC - / ADC8 ADC6 / ADC0 Bit 5 ADLAR - ADATE - / ADC7 ADC5 / - Bit 4 - ADASCR ADIF - / ADC6 ADC4 / - Bit 3 MUX3 ADTS3 ADIE - / ADC5 ADC3 / - Bit 2 MUX2 ADTS2 ADPS2 - / ADC4 ADC2 / - Bit 1 MUX1 ADTS1 ADPS1 ADC9 / ADC3 ADC1 / - Bit 0 MUX0 ADTS0 ADPS0 ADC8 / ADC2 ADC0 / Page page 194 page 196 page 195 page 198 page 198 Monitor Stop Mode Control Register Monitor Data Register AC0IF - SPD4 - MSTR - - OCR0B4 OCR0A4 TCNT04 - COM0B0 - - EEAR4 EEDR4 - GPIOR04 - - GPIOR34 - - SPD3 - CPOL - - OCR0B3 OCR0A3 TCNT03 WGM02 - - EEAR11 EEAR3 EEDR3 EERIE GPIOR03 INT3 INTF3 GPIOR33 11 4378CS-AVR-09/08 Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name GPIOR2 GPIOR1 Reserved Reserved TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved PORTE DDRE PINE PORTD DDRD PIND - - - PORTB DDRB PINB Reserved Reserved Reserved Bit 7 GPIOR27 GPIOR17 - - - - - - - - - - - - - PORTD7 DDD7 PIND7 - - - PORTB7 DDB7 PINB7 - - - Bit 6 GPIOR26 GPIOR16 - - - - - - - - - - - - - PORTD6 DDD6 PIND6 - - - PORTB6 DDB6 PINB6 - - - Bit 5 GPIOR25 GPIOR15 - - ICF1 - - - - - - - - - - PORTD5 DDD5 PIND5 - - - PORTB5 DDB5 PINB5 - - - Bit 4 GPIOR24 GPIOR14 - - - - - - - - - - - - - PORTD4 DDD4 PIND4 - - - PORTB4 DDB4 PINB4 - - - Bit 3 GPIOR23 GPIOR13 - - - - - - - - - - - - - PORTD3 DDD3 PIND3 - - - PORTB3 DDB3 PINB3 - - - Bit 2 GPIOR22 GPIOR12 - - OCF1B OCF0B - - - - - - PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 - - - PORTB2 DDB2 PINB2 - - - Bit 1 GPIOR21 GPIOR11 - - OCF1A OCF0A - - - - - - PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 - - - PORTB1 DDB1 PINB1 - - - Bit 0 GPIOR20 GPIOR10 - - TOV1 TOV0 - - - - - - PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 - - - PORTB0 DDB0 PINB0 - - - Page page 25 page 25 page 122 page 94 page 73 page 73 page 73 page 73 page 73 page 73 - - - page 72 page 72 page 73 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 12 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 6. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 13 4378CS-AVR-09/08 Mnemonics SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Operands P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Description Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK Flags None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 BIT AND BIT-TEST INSTRUCTIONS DATA TRANSFER INSTRUCTIONS Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack MCU CONTROL INSTRUCTIONS 14 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 Mnemonics NOP SLEEP WDR BREAK Operands Description No Operation Sleep Watchdog Reset Break Operation (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Flags None None None None #Clocks 1 1 1 N/A 15 4378CS-AVR-09/08 7. Ordering Information Speed (MHz) 16 16 Note: Note: Power Supply 2.7 - 5.5V 2.7 - 5.5V Ordering Code AT90PWM1-16SU AT90PWM1-16MU Package SO24 QFN32 Operation Range Extended (-40C to 105C) Extended (-40C to 105C) All packages are Pb free, fully LHF This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 16 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 8. Package Information Package Type SO24 QFN32 24-Lead, 0.300" Body width, Plastic GullWing Small Outline Package (SOIC) 32-Lead, Quad Flat No lead 17 4378CS-AVR-09/08 8.1 SO24 18 AT90PWM1 4378CS-AVR-09/08 AT90PWM1 8.2 QFN32 19 4378CS-AVR-09/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4378CS-AVR-09/08 |
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